Job Description

Join an ambitious and highly experienced team of silicon and hyperscale data center systems experts as a Physical Design Engineer. Our team is motivated by a singular mission: to revolutionize the performance and scalability of next-generation distributed computing infrastructure. You have the opportunity to build a groundbreaking new category of product, working alongside some of the industry's most talented hardware and software engineers to create truly disruptive infrastructure solutions that delight our customers. We are looking for talented, motivated engineers with experience in physically implementing large-scale networking and computing semiconductor products, and who are looking to grow in a fast paced, dynamic startup environment. We seek experienced physical design engineers capable of contributing across the entire chip development lifecycle, including CAD tool flow setup, early floorplanning in conjunction with microarchitecture development, block partitioning, power planning, clock network design, P+R, timing closure, package design, PI/SI analysis, physical verification, and tapeout. Roles and Responsibilities Build and support the CAD tool flow for physical implementation in a cloud-first development environment. Collaborate with architects and microarchitects on chip-level floorplanning and block partitioning, evaluating tradeoffs in functional partitioning, block size, and interface complexity with stakeholders. Define and develop major physical structures, including clock and reset architectures, power delivery networks, and interconnect topologies. Execute physical implementation at block, cluster, and top levels, from synthesis, floorplanning, power planning, through P+R, timing closure, physical verification, and tapeout. Coordinate with foundry and library partners on 3rd party IP and process technology issues, including device model updates, IP integration, and pre-tapeout signoff. Skills and Qualifications Proven industry experience with a successful track record in physical implementation of large, high-performance network fabrics (Ethernet, Infiniband, HPC), NICs, Smart-NICs, CPUs, or GPUs in the latest silicon process nodes. Deep expertise with CAD tools such as Cadence Genus, Innovus, Synopsys ICC2/FusionCompiler, Tempus, PrimeTime SI/PX, StarRC, ICV, Calibre throughout the physical design workflow. Strong familiarity with analysis tools like Redhawk and Voltus. Experience with circuit analysis using HSPICE is a plus. Expertise in SystemVerilog and scripting languages such as Perl, Python. Minimum BSEE/CE with 10+ years or MSEE/CE with 5+ years of industry experience. Proven track record of delivering high-volume shipped products. Company Background We are a well-funded, stealth-mode startup based in Mountain View, CA, founded by senior executives from leading infrastructure semiconductor and hyperscale cloud companies, backed by top-tier investors. Our diverse team of chip/software/system architects and developers excel in hardware/software co-design. We have built and delivered technologies that handle over half of the world's global data center traffic. Additional Questions What was the process node for your most recent tapeout? How many placeable instances were in the largest block you have worked on? #J-18808-Ljbffr Enfabrica

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